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CXA2125Q
Audio/Video Switch with Electronic Volume for 3 Scart
Description The CXA2125Q is an I2C programmable audio, video switch designed primarily for set top box applications. It interfaces from digital encoder sources to TV, VCR and auxiliary scart connectors. Features * 3 scart independent audio/video switching (TV, VCR, AUX) * 0 to -63dB volume control with click noise reduction * 5 stereo audio inputs * I2C control * Scart Function Switching input and output * Scart Fast Blanking for OSD * Mono switchable to stereo on TV, VCR and AUX outputs * On-chip +12V to +9V voltage regulator * Logic output * Selectable +6dB, +12dB gain on TV output * RGB input on VCR scart * Compatible with 2 scart Audio/Video switch CXA2126Q Applications Digital Set Top Box Structure Bipolar silicon monolithic IC Absolute Maximum Ratings * Supply voltage VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD Operating Conditions * Supply voltage * Operating voltage 64 pin QFP (Plastic)
12 -20 to +75 -65 to +150 850
V C C mW
10.7 to 12 9 0.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E99338-PS
CXA2125Q
Block Diagram
Typical Connection Typical Connection
DIG VCR AUX DIG BLUE VCR BLUE AUX BLUE DIG GREEN/CVBS VCR GREEN AUX GREEN DIG RED/CHROMA DIG CHROMA VCR RED/CHROMA AUX RED/CHROMA DIG CVBS/LUMA DIG CVBS/LUMA VCR CVBS/LUMA AUX CVBS/LUMA TV CVBS
FBLK_IN1 52 FBLK_IN2 53 FBLK_IN3 51 VIN1 63 VIN2 61 VIN3 13 VIN4 2
FBLK_SW +5V 0V 100 50 TV_FBLANK
VIDEO_SWITCH1 (TV) x2 100 48 VOUT1 TV BLUE
VIN5 59 VIN6 15 VIN7 VIN8 4 6
x2
100 47 VOUT2 TV GREEN TV
VIN9 57 VIN10 17 VIN11 8
x2
100 46 VOUT3 TV RED/C
VIN12 10 VIN13 55 VIN14 21 VIN15 23 VIN16 25 VIDEO_SWITCH2 (VCR)
x2
100 49 VOUT4 TV CVBS/Y
ANALOGUE SAT CVBS
VID_VCC 60 VID_BIAS 62 VID_GND 7
4.05V Bias 1
x2
100 41 VOUT5 VCR CHROMA VCR
AUD_VCC 20 AUD_BIAS 19 AUD_GND 26 DIG_VCC 38 DIG_GND 43 VCC_12V 58 VREG_BASE 56 VREG_9V 54
4.5V Bias 2
x2
100 44 VOUT6 VCR CVBS/Y
VIDEO_SWITCH3 (AUX) x2 9V reg x2 Bias VOLUME CONTROL AUDIO_SWITCH1 (TV) & MUTE x2 x2 8dB 1dB 0/6dB TV x2 8dB -6dB -6dB -6dB -6dB AUDIO_SWITCH2 (VCR) x2 1dB 0/6dB MONO SWITCH x2 42 LTV ZCD 33 MONO 100 39 VOUT7 AUX CVBS AUX
DIG VCR AUX TV ANALOGUE SAT
RIN1
3 -6dB -6dB -6dB -6dB
35 PHONO_R
RIN2 12 RIN3 16 RIN4 22 RIN5 27
40 RTV
DIG VCR AUX TV ANALOGUE SAT
LIN1
5
37 PHONO_L
LIN2 14 LIN3 18 LIN4 24 LIN5 29
Selectable Gain Stage
34 ROUT1 VCR
x2 MONO SWITCH
36 LOUT1
AUDIO_SWITCH3 (AUX) x2
31 ROUT2 AUX
x2 MONO SWITCH Bias 4.5V HW_MUTE 45 FNC_VCR 64 FNC_AUX 1 Monitor Monitor Mute
32 LOUT2
I2C Interface LOGIC P.O.D 3.3V or 5V
30 FNC_TV
28 LOGIC
SDA 11 SCL 9
-2-
CXA2125Q
Pin Configuration
TV_FBLANK
HW_MUTE
FBLK_IN3
DIG_GND
DIG_VCC
PHONO_R
PHONO_L
VOUT4
VOUT1
VOUT2
VOUT3
VOUT6
VOUT5
VOUT7
ROUT1
LOUT1
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
FBLK_IN1 52 FBLK_IN2 53 VREG_9V 54 VIN13 55 VREG_BASE 56 VIN9 57 VCC_12V 58 VIN5 59 VID_VCC 60 VIN2 61 VID_BIAS 62 VIN1 63 FNC_VCR 64
RTV
LTV
MONO 32 LOUT2 31 ROUT2 30 FNC_TV 29 LIN5 28 LOGIC 27 RIN5 26 AUD_GND 25 VIN16 24 LIN4 23 VIN15 22 RIN4 21 VIN14 20 AUD_VCC AUD_BIAS
1 FNC_AUX
2 VIN4
3 RIN1
4 VIN7
5 LIN1
6 VIN8
7 VID_GND
8 VIN11
9 10 11 12 13 14 15 16 17 18 19 SDA VIN10 VIN12 RIN2 VIN3 LIN2 VIN6 RIN3 LIN3 SCL
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CXA2125Q
Pin Description Pin No. 63 61 13 2 59 15 4 6 57 17 8 10 55 21 23 25 Symbol VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15 VIN16 Pin voltage Equivalent circuit Description
VCC = 12V 63 4 61 6 13 57 120k 147 14A
VCC = 9V
4.6V
2 17 59 8 15 10 55 21 23 25
Video signal inputs. An input coupling capacitor is required. (typ = 0.47F)
60A
VCC = 12V
12 16 22 27 14 18 24 29
RIN2 RIN3 RIN4 RIN5 LIN2 LIN3 LIN4 LIN5 4.5V
4.5V 12 14 16 18 22 24 27 29 33k 33k
Audio signal inputs. An input coupling capacitor is required. (typ = 2.2F)
7A
VCC = 12V
VCC = 9V 200 140A 100
48 47 46 49 41 44 39
VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7
48 47 46
3.9V
49 41 44 39 280A
Video signal outputs.
-4-
CXA2125Q
Pin No.
Symbol
Pin voltage
VCC = 12V
Equivalent circuit
Description
VCC = 9V 33A
40 34 31 42 36 32 35 37 33
RTV ROUT1 ROUT2 LTV LOUT1 LOUT2 PHONO_R PHONO_L MONO
35 31
22k 20k 55 33A 20k
4.5V
37 42 33 36 40 32 34
Audio signal outputs. A coupling capacitor may be used. (typ = 10F)
VCC = 12V
VCC = 9V 14A 11k
62
BIAS_ VIDEO
3.9V
62 200 9k
Reference Bias for video circuit. Connected to GND with capacitor. (typ = 47F)
VCC = 12V
VCC = 9V
20k
19
BIAS_ AUDIO
4.5V
19 20k 7A
Reference Bias for audio circuit. Connected to GND with capacitor. (typ = 22F)
VCC = 12V 120 15k
30
FNC_TV
--
30
I2C controlled output giving 0V, 6V or 12V.
3k
-5-
CXA2125Q
Pin No.
Symbol
Pin voltage
VCC = 12V
Equivalent circuit
Description
77.7k
54
VREG_9V
9V
54 13.5k 120A
Pin connected to emitter of external regulator transistor.
VCC = 12V 1mA
VCC = 12V
56
VREG_ BASE
56
9.7V
413 15pF 120A
Connection to base of external regulator transistor. Max I = 1mA
VCC = 9V 40A
4k
9
SCL
--
9 40k 10k
I2C clock input.
VCC = 9V 40A
4k
11
SDA
--
11 40k 4.5k
I2C data input/output.
-6-
CXA2125Q
Pin No.
Symbol
Pin voltage
VCC = 12V
Equivalent circuit
Description
45
HW_MUTE
--
147 45
72k
28k
HW MUTE: This pin is active high > 2.5V < 9V. When high, all audio muted.
VCC = 12V
VCC = 9V 3V 8A 40k
28
LOGIC
--
28 4.5k 7.5k
Open collector logic pins.
VCC = 12V 100 100A
VCC = 9V
50
FBLK_ OUT
--
100 50
100A
Fast Blank output set by I2C to input FBLK_IN1, FBLK_IN2, or FBLK_IN3. High = 5.3V Low = 1.2V Connected to external emitter follower.
VCC = 12V 50A
VCC = 9V
52 53 51
FBLK_IN1 FBLK_IN2 FBLK_IN3
--
52 53 51 147 90A
Fast Blank inputs. Low = < 0.4V High = > 1.0V, < 3.0V
-7-
CXA2125Q
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC = 9V 80A 12.5k 12.5k
64 1
FNC_VCR FNC_AUX
--
64 1 10k 25k
Function switching input. (Scart pin 8)
VCC = 12V 4.5V 33k
3 5
RIN1 LIN1
4.5V
3 5
Audio signal inputs. A coupling capacitor is required for these inputs. (typ = 2.2F)
7A
-8-
CXA2125Q
Electrical Characteristics Nominal conditions (Ta = 25C) Item Current consumption Video system Item Input pin voltage Output pin voltage - with output on. Output pin voltage - with output off. Gain Bandwidth Input dynamic range Output dynamic range Cross talk S/N ratio Symbol VVPin VVPout1 VVPout2 GVv fV3dB VDRVI VDRVO Vctv S/NV Symbol ICC Conditions VCC_12V = 12V, No signal, no load Min. 30 Typ. 50 Max. 80 Unit mA
Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V) Conditions No signal, no load (Fig.1) No signal, no load (Fig.1) No signal, no load (Fig.1) f = 200kHz, 0.3Vp-p input (Fig.2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB (Fig. 2) 200kHz input (Fig.2) 200kHz, 2.5Vp-p input (Fig.2) f = 4.43MHz, 1Vp-p input (Fig.2) Ratio of 0.7Vp-p white video signal to "black line" noise. Weighted using CCIR 567. HPF @5kHz, LPF @5MHz. (Fig.2) 1Vrms 1kHz input through 56k. Attenuation measured to calculate ZinV (Fig.3)
Input Pin V Plus
Min. 4.3 3.6 -- 5.5 15 2.5 5.0 -- --
Typ. 4.6 3.9 0 6.0 20 -- -- -- 72
Max. 4.9 4.2 0.2 6.5 -- -- -- -50 --
Unit V V V dB MHz Vp-p Vp-p dB dB
Input impedance
ZinV
94
120
175
k
V1
V2
Non-linearity
Lin V1 = Pin voltage +0.5V, V2 = Pin voltage +1V At output, non-linearity =
(Fig.4)
-3
-0.4
3
%
V2 -1 x 100 V1 x 2
Differential gain Differential phase Sync crush
DG DP SC
1.7Vp-p 5-step modulated staircase. (Chroma and Burst are 150mVp-p 4.43MHz) (Fig.2) as above. (Fig.2) Percentage reduction in sync pulse (0.4Vp-p), with tip at -1.2V input offset. (Fig.4)
-3 -3 -2
1.5 1 0
2 2 2
% Deg %
-9-
CXA2125Q
Audio system Unless otherwise stated: input coupling capacitor 1F; output coupling capacitor of 10F; load of 10k. Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V) Item Input/output pin voltage Gain Input RIN1/LIN1 RIN1/LIN1 RIN1/LIN1 RIN1 + LIN1 RIN1 + LIN1 RIN1 + LIN1 RIN2, 3, 4, 5 LIN2, 3, 4, 5 RIN2, 3, 4, 5 LIN2, 3, 4, 5 Output TV/Phono TV/Phono VCR/AUX TV mono TV mono VCR mono AUX mono TV/Phono TV/Phono GVA1 GVA2 GVA3 GVA4 GVA5 GVA6 GVA7 GVA8 GVA9 GVA10 GVA11 GVA12 FAF f = 1kHz, 0.5Vrms input. TV output amplifier set to 0dB (Fig. 6) f = 1kHz, 0.5Vrms input. TV output amplifier set to +6dB (Fig. 6) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 0.5Vrms stereo input. TV output amplifier set to 0dB (Fig. 6) f = 1kHz, 0.5Vrms stereo input. TV output amplifier set to +6dB (Fig. 6) f = 1kHz, 0.5Vrms stereo input. (Fig. 6) f = 1kHz, 1Vrms input. TV output amplifier set to 0dB (Fig. 6) f = 1kHz, 1Vrms input. TV output amplifier set to +6dB (Fig. 6) f = 1kHz, 1Vrms stereo input. TV output amplifier set to 0dB (Fig. 6) f = 1kHz, 1Vrms stereo input. TV output amplifier set to +6dB (Fig. 6) f = 1kHz, 1Vrms input. (Fig. 6) f = 1kHz, 1Vrms stereo input. (Fig. 6) 0.3Vp-p input. Output level at 30kHz with 1kHz serving as 0dB. (Fig. 7) 0.3Vp-p input; frequency where output level is -3dB with 1kHz serving as 0dB. No load (Fig. 7) f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @80kHz. (Fig. 6) f = 1kHz (Fig. 6) f = 1kHz (Fig. 6) f = 1kHz, 1Vrms input on one input, measure on any other audio output. (Fig.6) 5.5 11 -- -- -- -- -0.5 5.5 -0.7 5 -0.5 -0.7 -0.3 6 12 6 6 12 6 0 6 0 6 0 0 0 6.5 13 -- -- -- -- +0.5 6.5 +0.3 7 +0.5 +0.3 +0.3 dB dB dB dB dB dB dB dB dB dB dB dB dB Symbol VAPIN Conditions No signal, no load (Fig. 5) Min. 4.2 Typ. 4.5 Max. 4.8 Unit V
RIN2, 3, 4, 5 TV mono + LIN2, 3, 4, 5 RIN2, 3, 4, 5 TV mono + LIN2, 3, 4, 5 RIN2, 3, 4, 5 LIN2, 3, 4, 5 VCR/AUX
RIN2, 3, 4, 5 VCR mono + LIN2, 3, 4, 5 AUX mono Audio frequency response
Frequency B/W
FBWA1
--
1
--
MHz
Distortion Input dynamic range RIN2, 3, 4, 5 LIN2, 3, 4, 5 Input dynamic range RIN1 LIN1 Cross talk (Channel separation)
THD VdA1 VdA2
-- 2 1
0.003 -- --
0.2 -- --
% Vrms Vrms
VctA
--
--
-76
dB
- 10 -
CXA2125Q
Item DC offset Input impedance RIN2, 3, 4, 5 LIN2, 3, 4, 5 Input impedance RIN1/LIN1 Output impedance Phase difference
Symbol Voff Zin1 Zin2 Zout Vpda
Conditions Offset voltage between input and output (Fig. 5) (excluding any external series resistor) (excluding any external series resistor) (excluding any external series resistor) f = 1kHz, 1Vrms input to two channels. Phase difference of stereo output measured f = 1kHz, 1Vrms input (at maximum volume). HPF @20Hz, LPF@20kHz. (Fig. 6)
Min. -30 -- -- -- --
Typ. -- 66 33 10 0.05
Max. +30 -- -- -- --
Unit mV k k Deg
S/N ratio Electronic Volume Control Fine volume attenuation step Coarse volume attenuation step Mute DC Offset -RTV, LTV
S/NA
80
90
--
dB
AEVC AEVF Amute VoffTV
f = 1kHz, 0.5Vrms input. Set by I2C. (Fig.6) f = 1kHz, 0.5Vrms input. Set by I2C. (Fig.6) f = 1kHz, 1Vrms input. (Fig.6) Offset voltage between any audio input and RTV, LTV outputs. (Fig.5)
0.6 7.5 -- -30
1 8 -- 0
1.4 8.5 -80 +30
dB dB dB mV
- 11 -
CXA2125Q
I2C Electrical Characteristics Nominal conditions (Ta = 25C, Vcc_12V = 12V, VREG_9V = 9V) Item High level input voltage Low level input voltage Low level output voltage Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width Symbol VIH VIL VOL fSCL With SDA, 3mA current supplied Conditions Min. 2.3 0 0 0 4.5 4.0 4.7 4.0 4.7 5 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 100 -- -- -- -- -- -- -- 1 300 -- Unit V V V kHz s s s s s s ns s ns s
tBUF tHD;STA
tLOW High level clock pulse width tHIGH
Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation
tSU;STA tHD;DAT tSU;DAT tR tF tSU;STO
- 12 -
CXA2125Q
V
+12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k Measurement point
+9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 +12V +9V 53 54 55 56 57 58 59 +9V 60 61 62 63 64 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA CXA2125Q BC547B
32 31 30 29 28 27 26 25 24 23 22 21 20 +9V
22F
V
Measurement point
Fig. 1. Video system (d.c. test) d.c. measured from pins: 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 39, 41, 44, 46, 47, 48, 49, 55, 57, 59, 61, 63 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests.
- 13 -
CXA2125Q
V
+12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k Measurement point
+9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 +12V 75 2.2F 75 2.2F +9V 53 54 55 56 57 75 2.2F 75 +9V 2.2F 75 2.2F 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 2.2F 58 59 60 61 62 63 64 CXA2125Q BC547B
32 31 30 29 28 27 26 25 24 23 22 21 20 2.2F 2.2F +9V 75 2.2F 75 75
75 2.2F
75 2.2F
75 2.2F
75 2.2F
75 2.2F
75 2.2F
75 2.2F
22F
Input signal
Fig. 2. Video system (gain, dynamic range, bandwidth, differential gain, differential phase, crosstalk, signal to noise) Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. For tests requiring video measuring equipment with 75 input impedance, an external video line driver or buffer is used. 3. All video outputs are loaded with emitter follower during tests. - 14 -
75
CXA2125Q
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 +12V 56k 2.2F 56k 2.2F +9V 53 54 55 56 57 56k 2.2F +9V 2.2F 56k 2.2F 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA 2.2F 58 59 56k 60 61 62 63 64 CXA2125Q BC547B
32 31 30 29 28 27 26 25 24 23 22 21 20 +9V 2.2F 2.2F 56k 2.2F 56k 56k
56k 2.2F
56k 2.2F
56k 2.2F
56k 2.2F
56k 2.2F
56k 2.2F
56k 2.2F
22F
1kHz
Input signal
56k
V
Measurement point
Fig. 3. Video system (input impedance)
Signal applied and measured from Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. Voltage measurements carried out with a high input impedance DVM. Typically 10G.
- 15 -
CXA2125Q
V
+12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k +12V BC547B 1k Measurement point
+9V 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 +12V +9V 53 54 55 56 57 58 59 +9V 60 61 62 63 64 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA CXA2125Q BC547B
32 31 30 29 28 27 26 25 24 23 22 21 20 +9V
22F
PSU
Input signal
Fig. 4. Video system (linearity) Signal applied to Pins 2, 4, 6, 8, 10, 13, 15, 17, 21, 23, 25, 55, 57, 59, 61, 63 Output signal measured from Pins 39, 41, 44, 46, 47, 48, 49 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. All video outputs are loaded with emitter follower during tests.
- 16 -
CXA2125Q
Output measurement point
V
HW mute +5V 1k SW1 +9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52 +12V +9V 53 54 55 56 57 58 59 +9V 60 61 62 63 64 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL SDA CXA2125Q BC547B
32 31 30 29 28 27 26 25 24 23 22 21 20 +9V
22F
V
Input measurement point
Fig. 5. Audio system (d.c. tests) d.c. measured from pins: 3, 5, 12, 14, 16, 18, 22, 24, 27, 29, 31, 32, 33, 34, 35, 36, 37, 40, 42 Note) All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor.
- 17 -
CXA2125Q
Measurement point
10F
10F
+5V 1k SW1
10F
HW mute
V
10k
10F
10F
10F
+9V
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10F 10F 2.2F 600
52 +12V +9V 53 54 55 56 57 58 59 +9V 60 61 62 63 64 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL 600 2.2F 600 2.2F SDA 600 2.2F 600 2.2F 600 2.2F 600 2.2F 22F CXA2125Q BC547B
10F
32 31 30 29 28 27 26 25 24 23 22 21 20
2.2F 600
600 2.2F 600 2.2F +9V
Input signal
Fig. 6. Audio system (gain, dynamic range, signal to noise, crosstalk, distortion, volume control) Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. When muting audio using hardware mute, SW1 is closed.
- 18 -
CXA2125Q
Measurement point
V
10F 10F 10F 10F HW mute +5V 1k SW1 +9V
10F
10F
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 10F 10F 2.2F 600
52 +12V +9V 53 54 55 56 57 58 59 +9V 60 61 62 63 64 47F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCL 600 2.2F 600 2.2F SDA 600 2.2F 600 2.2F 600 2.2F 600 2.2F 22F CXA2125Q BC547B
10F
32 31 30 29 28 27 26 25 24 23 22 21 20
2.2F 600
600 2.2F 600 2.2F +9V
Input signal
Fig. 7. Audio system (bandwidth) Signal applied to Pins, 3, 5, 12, 14, 16, 18, 22, 24, 27, 29 Output signal measured from Pins 31, 32, 33, 34, 35, 36, 37, 40, 42 Notes) 1. All +9V supplies de-coupled close to supply pins, 20, 38, 60 with 10nF ceramic capacitor. 2. When muting audio using hardware mute, SW1 is closed.
- 19 -
Application Circuit
+12V
75
BC547B
75 10F Phono Outputs L R RF Modulator 10nF
BC547B
75
BC547B BC547B 75 1k 1k +12V BC547B 75 560 560 MONO 10F 10F 10F 560 560
75
1F
1F
20 18 16 14 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
1k
1k
TV SCART
BC547B LOUT1 FBLK_IN3 VOUT4 VOUT1 VOUT2 VOUT3 VOUT6 LTV RTV VOUT7 DIG_VCC ROUT1 75 1k 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 FBLK_IN1 52 53 54 55 56 57 58 59 60 61 62 63 64 30 29 28 27 31 32 FBLK_IN2 VREG_9V 2.2F VIN13 +12V VREG_BASE BC547B +12V VIN5 VID_VCC 2.2F VIN2 VID_BIAS 47F FNC_VCR VIN1 10F 10nF VCC_12V VIN9 2.2F LOUT2 ROUT2 FNC_TV LIN5 LOGIC RIN5 26 25 24 23 22 21 20 AUD_GND VIN16 LIN4 VIN15 RIN4 VIN14 AUD_VCC 2.2F 2.2F 1F 10k 1F
PHONO_L 10F
TV_FBLANK
HW_MUTE
DIG_GND 10F
VOUT5 560 10F
PHONO_R 560 10F
Audio L
SCL
SDA
VIN7
LIN1
VIN8
VIN3
LIN2
VIN4
RIN1
RIN2
VIN6
RIN3
VIN11
FNC_AUX
VID_GND
75 10k 1F 1F 2.2F 2.2F
20 18 16 14 12 10 8 6 4 2 1 2 3 4 5 6 7 8 BC547B 1k 2.2F 2.2F
21 19 17 15 13 11 9 7 5 3 1
75 22F 2.2F 2.2F
AUD_BIAS
75
1k
VIN12
VIN10
LIN3
- 20 -
2.2F
Audio R
CXA2125Q
CVBS
Analogue Satellite
75
+12V
BC547B 9 10 11 12 13 14 15 16 17 18 19 10F 10nF
75
75
20 18 75 16 14 75 12 10 8 6 4 2
21 19 17 15 13 11 9 7 5 3 1
VCR SCART
FAST BLANK AUDIO R AUDIO L BLUE
AUX SCART
GREEN RED CHROMA CVBS LUMA I 2C 10k 75 75 75
1F 1F
Digital Encoder
CXA2125Q
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA2125Q
Description of Operation 1. Explanation of Video Section The video section comprises of 16 high impedance inputs switched through to 7 video outputs. A +6dB internal amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation which occurs at the external emitter follower stage used for driving video loads. All video outputs have an integrated 100 series protection resistor. The typical external configuration is shown in Fig. 1-1.
VID_VCC = 9V Scart In 75 0.47F Switch 100 Amp 75 120k Vbias 1k 75 BC547B 75 Load +12V Scart Out
Vbias Video Element
Fig. 1-1. Video Circuit Element: 6dB gain amplifier with external emitter follower Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output dc voltage is approximately 0V and hence the current consumption of the external emitter followers is reduced.
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CXA2125Q
2. Explanation of Audio System Inputs and Outputs The audio system consists of 5 stereo inputs, 3 stereo outputs and separate mono and phono outputs. The stereo outputs can be connected to any one of the 5 stereo inputs. All audio inputs have a -6dB attenuator except RIN1 and LIN1. Thus, the net gain of the audio system is 0dB, as the internal switch is followed by an audio amplifier having +6dB of gain. The stereo input RIN1/LIN1 does not have an input attenuator and therefore the net gain from input to output is +6dB. The output impedance of each audio amplifier is near zero, and can be capacitively coupled directly to the external scart circuit. The output circuitry is typically a 10F capacitor, and an optional 560 series compliance resistor. Depending on the length and type of cable used in the scart cable connector, the load seen at the scart terminal will consist of a parallel capacitor, (100pF to 400pF) and mandatory 10k resistor connected to ground. The customer may chose to place an alternative audio filter at the AV switch output. TV Audio Output The TV audio section is composed of an audio switch followed by two variable gain stages, corresponding to the coarse and fine electronic volume control. The coarse volume control gives a 0 to -56dB range in 8dB steps. Similarly the fine control gives a 0 to -7dB range in 1dB steps. The volume control section is followed by a switchable 0/+6dB amplifier which allows compensation for low level signals from a DAC. Finally, a mono switch allows the mixed R + L signal to be switched to the R and L output channels. (Fig. 2-1)
TV Audio Output 1F RIN1
3 -6dB -6dB -6dB -6dB
RIN2 12 Audio RIN3 16 Source RIN4 22 RIN5 27 LIN1 5
Volume Control
x2
35 PHONO_R
RTV x2 8dB 1dB 0/6dB x2 ZCD 40 560
Scart Pin 10F C
LIN2 14 LIN3 18 LIN4 24 LIN5 29
-6dB -6dB -6dB -6dB Mute 8dB 1dB 0/6dB
MONO SWITCH
42 LTV Optional Low Pass Filter 37 PHONO_L
x2
Fig. 2-1. TV Audio Output TV Mute The I2C mute function acts only on the TV, phono and mono audio circuit. Audio mute can be implemented after a audio zero cross detection to reduce click noise, or immediately depending on the I2C setting of ZCD. It can be seen from the I2C write format that the same mute bit occurs in DATA 1 and DATA 7. This allows the software to action an immediate mute, make any suitable changes to the audio source or electronic volume control and after a minimum period of 6 x 90s (540s) un-mute the output buffer. Such a period provides ample time to allow any transient ac voltages to settle during an audio source change. - 22 -
CXA2125Q
Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The change volume or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. The zero cross detection circuit can be turned off by setting the "ZCD" bit low in the I2C write mode. Hardware Mute A hardware mute pin is provided which will mute all audio outputs when the pin voltage exceeds 2.5V. This muting is instantaneous. VCR and AUX Output The outputs ROUT1, 2 and LOUT1, 2 have a fixed gain of 0dB from the input. If any attenuation is required then it is possible to insert a series resistance on the input. (Fig. 2-2)
VCR and AUX Audio Circuit 1F RIN1
3 -6dB -6dB -6dB -6dB x2 -6dB -6dB -6dB -6dB Mute MONO SWITCH 36
*
RIN2 12 Audio RIN3 16 Source RIN4 22 RIN5 27 LIN1 5
x2
34 ROUT1/2
*
Scart Pin 10F C
31
560
LIN2 14 LIN3 18 LIN4 24 LIN5 29
32
LOUT1/2 Optional Low Pass Filter
Fig. 2-2. VCR and AUX Audio Output Phono Outputs There is a stereo phono output which carries the same signal as the TV output. This is typically used for connection to a hi-fi. The user may connect an external attenuator which is a.c. coupled to the outputs.
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CXA2125Q
I2C Data Interface Table IC Control Data Format S Slave address A S: Start condition Address = 90H I2C Data Structure (write mode) b7 Address Data1 Data2 Data3 Data4 Data5 Data6 Data7 Not used Vout5 Mute Not used Not used Not used TV Aud Mute 1 b6 0 EVC Not used Not used Not used Not used Vout7 on/off TV Aud Gain Vout6 on/off mono AUX Vid_Switch 1 TV Vid_Switch 2 VCR Vid_Switch 3 AUX FBLK Vout5 on/off mono VCR Vout4 on/off mono TV Vout3 on/off Not used b5 0 b4 1 b3 0 EVF b2 0 b1 0 TV Aud Mute Aud_Switch 1 TV Aud_Switch 2 VCR Aud_Switch 3 AUX FNC Vout2 on/off Not used LOGIC Vout1 on/off Not used b0 0 = Write Z.C.D DATA1 A DATA2 A DATA3 A DATA4 A DATAn A P
A: Acknowledge
P: Stop condition
Key EVC: EVF: TV Aud Mute: Z.C.D: Vid_Switch 1: Vid_Switch 2: Vid_Switch 3: Aud_Switch 1: Aud_Switch 2: Aud_Switch 3: FNC: FBLK: LOGIC:
Electronic Volume Course (8dB steps) Electronic Volume Fine (1dB steps) TV Audio mute. Controls the TV audio output buffer. (Same bit appears in data 1 & 7) Zero cross detector active. When ZCD = 1 volume and mute change at zero cross. Selects the input video sources for Vout1, Vout2, Vout3, Vout4 Selects the input video sources for Vout5, Vout6 Selects the input video sources for Vout7 Selects one of 5 stereo inputs for RTV, LTV, PHONO_L, PHONO_R, MONO Selects one of 5 stereo inputs for Rout1, Lout1 Selects one of 5 stereo inputs for Rout2, Lout2 Video function switch control Video Fast Blanking control Logic outputs (open collector). 0 = high impedance. 1 = current sink mode.
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CXA2125Q
I2C Data Format (read mode) S Slave address A NA: No Acknowledge I2C Data Structure (read mode) b7 Address Data Key FNC_VCR: FNC_AUX: ZC Status: P.O.D.: 1 x b6 0 x b5 0 ZC Status b4 1 P.O.D. b3 0 FNC_AUX b2 0 b1 0 b0 1 = Read FNC_VCR DATA8 NA P
At Pin 64, AV switch monitors the voltage of pin 8 from VCR scart, and records status. At Pin 1, AV switch monitors the voltage of pin 8 from AUX scart, and records status. ZC Status = 1 indicates that zero cross condition has been achieved after the ZCD is turned on. Power On Detect. P.O.D. = 1 when DIG_VCC voltage rises above a threshold level of approximately 5V.
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CXA2125Q
3. Video Input I2C Control Switch 1 (TV Output) Switch setting 0 1 2 3 4 5 6 7 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx xx111xxx Data 2 Bits 3, 4, 5 Vout1 (B) VIN1 Bias VIN2 VIN3 Bias Bias Bias Bias Vout2 (Green) VIN4 Bias VIN5 VIN6 Bias Bias Bias Bias Vout3 (R/C) VIN7 VIN8 VIN9 VIN10 VIN7 Bias Bias Bias Vout4 (CVBS/Y) VIN11 VIN12 VIN13 VIN14 VIN4 VIN15 VIN16 Bias Comment Digital encoder Digital encoder VCR AUX Digital encoder TV Analogue satellite Video mute
Note) After power on all TV outputs are off and muted. Switch 2 (VCR Output) Switch setting 0 1 2 3 4 5 6 7 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx xx111xxx Data 3 Bits 3, 4, 5 Vout5 (Chroma (C)) VIN7 VIN8 VIN9 VIN10 VIN7 Bias Bias Bias Vout6 (CVBS/Y) VIN11 VIN12 VIN13 VIN14 VIN4 VIN15 VIN16 Bias Comment Digital encoder Digital encoder VCR AUX Digital encoder TV Analogue satellite Video mute
Note) After power on VCR outputs are off and muted. VCR Chroma Mute Data 3 Bit 7 0 x x x x x x x = Vout5 active. Connected to input specified in above table. 1 x x x x x x x = Vout5 muted (the output dc bias still remains).
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CXA2125Q
Switch 3 (AUX Output) Switch setting 0 1 2 3 4 5 6 7 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx xx111xxx
Data 4 Vout7 (CVBS) VIN11 Bias VIN13 VIN14 VIN4 VIN15 VIN16 Bias
Bits 3, 4, 5 Comment Digital encoder Video mute VCR AUX Digital encoder TV Analogue satellite Video mute
Note) After power up the AUX video outputs are off and muted. Standby Mode Control Data 6 Bits 0, 1, 2, 3, 4, 5, 6 Each video output can be individually turned off using data byte 6. 0 = Video output off 1 = Video output on Note) When switched off, the video outputs are high impedance to prevent d.c. driving of the external emitter follower stage. The reduction of overall current consumption will depend on how many video outputs are turned off. After power on all video outputs are in the off state.
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CXA2125Q
4. Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode 2. RGB mode
Scart pin voltage = 0 to 0.4V Scart pin voltage = 1 to 3.0V
Threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA2125Q, there are three fast blanking inputs, one associated with the Digital Encoder input (FBLANK_IN1), one with the VCR RGB/CVBS input (FBLANK_IN2), and another associated with the AUX RGB/CVBS input (FBLANK_IN3). These can be selected by I2C. In addition to the two blanking inputs, the fast blank pin output can be set to a constant 0V or 5V by means of the I2C control. Hence there are four possible states. These are controlled according to the following table. FBLK Control I2C Setting 0 1 2 3 4 5 6 7 xx000xxx xx001xxx xx010xxx xx011xxx xx100xxx xx101xxx xx110xxx xx111xxx 0V +5V Same level as Fast Blank in 1 (0/+5V) Same level as Fast Blank in 2 (0/+5V) Same level as Fast Blank in 3 (0/+5V) +5V +5V +5V Data 5 Bits 3, 4, 5 Fast Blank Output
Note) After power on the output is 0V. Fast Blank output circuit The output requires an external buffer stage to drive the required 75 scart termination. The levels at the IC output are 0V and +5V.
VCC
Fast Blank
0V/5V
75 Scart line 16 1k TV 75
CXA2125Q
Fig. 4-1. Fast Blanking Interface to TV SCART - 28 -
CXA2125Q
5. Function Switch, FNC. The function switch facility is designed to read the status of the SCART function pin 8 from the VCR input. The read register holds the status of the input function lines. The function output is controlled by I2C and is used to change the voltage on the function line to the TV. The output can be connected directly to the scart pin. (Fig. 5-1) Read Mode Reads the status of the inputs FNC_VCR and FNC_AUX. Input Pin Voltage FNC_VCR/FNC_AUX 0 to +2V (default) +4.5 to +7V +9.5 to +12V Level (SCART Defn.) (Internal TV) (16:9 External) (4:3 External) Read Data8 b1/b3 0 0 1 b0/b2 0 1 1
Write Mode Controls the voltage at the TV function line (pin 8) I2C Control (Data 5) 0 1 2 3 xxxxx00x xxxxx01x xxxxx10x xxxxx11x Mode/(Typical pin Voltage) Internal TV/(1V) External scart input 16:9 mode/(6V) External scart input 4:3 mode/(11V) External scart input 4:3 mode/(11V)
Note) After power on output is internal TV mode ie. 0V at the pin.
> 10V > 4.5V < 7V < 2V FNC_TV Scart Pin 8 10k CXA2125Q
Fig. 5-1. TV Function Switch Output
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CXA2125Q
6. Logic Output A single logical output pin is provided. This is controlled via the I2C and is an open collector output. Specification I2C bit 0 = open collector/high output impedance I2C bit 1 = Vsat (to 0.2V) Vmax at logic pin = 12V Imax during current sink = 1mA
LOGIC
Open collector logic outputs
I2C
Logic cct.
Fig. 6-1. Logic Output Interface
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CXA2125Q
7. I2C Audio Signal Control Outputs TV, VCR, AUX Switch Setting 0 1 2 3 4 5 6 7 xxxxx000 xxxxx001 xxxxx010 xxxxx011 xxxxx100 xxxxx101 xxxxx110 xxxxx111 Data 2, 3, 4 Bits 0, 1, 2 RTV, ROUT1, ROUT2 Rin1 Rin2 Rin3 Rin4 Rin5 Audio mute Audio mute Audio mute LTV, LOUT1, LOUT2 Lin1 Lin2 Lin3 Lin4 Lin5 Audio mute Audio mute Audio mute
Note) After power on the audio outputs are muted.
Volume Control Fine Setting 0 1 2 3 4 5 6 7 xxx000xx xxx001xx xxx010xx xxx011xx xxx100xx xxx101xx xxx110xx xxx111xx
Data 1 Bits 2, 3, 4 Volume Fine Control Gain 0dB -1dB -1dB -3dB -4dB -5dB -6dB -7dB
Volume Control Coarse Setting 0 1 2 3 4 5 6 7 000xxxxx 001xxxxx 010xxxxx 011xxxxx 100xxxxx 101xxxxx 110xxxxx 111xxxxx
Data 1 Bits 5, 6, 7 Gain 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB
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CXA2125Q
TV output amplifier Data 7 Bit 6 x 0 x x x x x x = 0dB x 1 x x x x x x = +6dB Note) After power on the gain is set to 0dB. TV Mono Switch Data 7 Bit 3 x x x x 0 x x x = Normal stereo output x x x x 1 x x x = Mono signal switched onto R + L line. VCR Mono Switch Data 7 Bit 4 x x x 0 x x x x = Normal stereo output x x x 1 x x x x = Mono signal switched onto R + L line. AUX Mono Switch Data 7 Bit 5 x x x 0 x x x x = Normal stereo output x x x 1 x x x x = Mono signal switched onto R + L line. Mute and Zero Cross Operation For TV, Phono and mono outputs. There are two mute control bits in the bus map to allow the TV outputs to be muted before the channel change instruction occurs. The normal structure for a click free audio channel change is as follows: Data 1 Mute the TV audio output with the ZCD switched on. Data 2 Change the TV audio source. Data 7 Un-mute the TV audio output again with the ZCD switched on. TV Aud Mute Data 1 Bit 1 Data 7 Bit 7 0 0 1 1
ZCD Data 1 Bit 0 0 1 0 1
RTV, LTV, Phono_R, Phono_L, Mono outputs Un-mute immediately Un-mute on next zero cross Mute immediately Mute on next zero cross
Note) After power on TV Mute and ZCD are set to 0.
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CXA2125Q
Notes on operation 1) Supply de-coupling capacitors, 10nF and 4.7F in parallel should be inserted as close to the supply pins, 20, 38, 60 as possible. 2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) Attention should be given to the electrolytic capacitors on the input and output signal pins. As the pin's voltage is between 3.7V and 4.7V dc the positive terminal on the capacitor should be orientated towards the pin. 4) The audio outputs may be muted at any time after power up by connecting the HW_MUTE pin (45) to a voltage > 2.5V and < 9V. 5) When driving video loads with impedance = 75 an emitter follower or video line driver is required to be connected at the video outputs as shown in the application schematic. Stray capacitance on pins Vout1-8 must be kept to a minimum by placing loads as close to the pins as possible. 6) The supply voltage on pin 58 "VCC_12V" should not exceed +12V. If the supply has poor regulation then a series diode or zener diode may be used to limit the voltage at this pin.
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CXA2125Q
Typical audio output distortion Inputs RIN1, LIN1 selected Inputs RIN2, 3, 4, 5/LIN2, 3, 4, 5 selected
1
0.1
THD [%]
0.1
THD [%] 0 0.5 1 Input [Vrms] 1.5
0.01
0.01
0.001
0.001
0.0001
0
1
2 Input [Vrms]
3
3.3
Audio frequency characteristics
4 Audio Output/Input gain [dB]
2
0
-2 Input = 0.3Vp-p -4
-6 100
1k
10k
100k Frequency [Hz]
1M
10M
8
Video frequency characteristics
Video Output/Input gain [dB]
6
4
2
0
100k
1M Frequency [Hz]
10M
50M
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CXA2125Q
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.2 M 0 to10
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
- 35 -
0.8 0.2
19
16.3

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